1. Field of the Invention
The present invention relates to a semiconductor memory device and a method for fabricating the same, and more particularly, to a semiconductor memory device having a storage node contact plug and a method for fabricating the same.
2. Description of the Related Art
In semiconductor memory devices such as DRAM (Dynamic Random Access Memory) devices, a variety of contact holes are employed, including for example, a pad contact hole, a bit line contact hole, a storage node contact hole, a metal contact hole and a via contact hole. Among these contact holes, the storage node contact hole is very small, because it must be formed in a narrow region between the bit lines, and difficult to form, because it is created by deeply etching an interlayer dielectric layer. Moreover, to form the storage node contact hole in the narrow region between the bit lines, high level and precise alignment skills are required in the photolithography process. It is very difficult to reproducibly form a storage node contact hole since an alignment margin of 30 nm or less is required for a design rule of 0.15 xcexcm or less.
Accordingly, a method for forming a storage node contact hole using a self-align contact etching process has been proposed. In the self-align contact etching process, after covering a bit line with a silicon nitride layer, the storage node contact hole is formed by etching an interlayer dielectric layer to be aligned at the silicon nitride layer, by taking advantage of the etching selectivity of the interlayer dielectric layer with respect to the silicon nitride layer. Next, a storage node contact plug material layer is formed in the storage node contact hole and then the storage node contact plug material layer is etched back, thereby forming a storage node contact plug. Thereafter, a storage node of a capacitor is formed on the storage node contact plug.
In highly integrated semiconductor memory devices, since the storage node is formed of a metal layer, the storage node plug material layer is also formed of a metal layer, such as a tungsten layer or a titanium nitride layer, in the self-align contact etching process.
However, when tungsten is used as the storage node contact plug material, the etching selection ratio (etching selectivity) of the storage node contact plug material layer (i.e., tungsten) with respect to the silicon nitride layer covering the bit line is poor. As a result, the storage node contact plug material layer made of tungsten is damaged, rather than being selectively etched. Such damage may cause a short circuit between the storage node contact plug and the bit line. Moreover, as the design rule decreases, the silicon nitride layer becomes thinner. Thus, if the silicon nitride layer is completely destroyed, margins for the self-align contact etching process are significantly decreased.
If the storage node contact plug material layer is formed of a titanium nitride layer, cracks may occur due to a large amount of stress at the titanium nitride layer when depositing the titanium nitride layer to have a thickness greater than a certain value. Moreover, the cracks may propagate to the interlayer dielectric layer, thereby causing serious problems.
To solve the above problems, it is a first object of the present invention to provide a semiconductor memory device which is capable of solving problems occurring when forming a storage node contact plug material layer comprising tungsten or titanium nitride.
It is a second object of the present invention to provide a method for fabricating the semiconductor memory device.
Accordingly, to achieve the first object, there is provided a semiconductor memory device. The semiconductor memory device includes a bit line stack, and a storage node contact hole aligned at bit line spacers formed at both side walls of the bit line stack and exposing a pad. In the storage node contact hole, a multi-layered storage node contact plug is formed by sequentially forming a first storage node contact plug and a second storage node contact plug.
Preferably, the first storage node contact plug is formed of a titanium nitride layer and the second storage node contact plug is formed of a polysilicon layer. An ohmic layer may be further formed on the pad and under the first storage node contact plug. A barrier metal layer, which acts as a third storage node contact plug, may be further formed on the second storage node contact plug.
According to another aspect of the present invention, a semiconductor memory device includes an interlayer dielectric layer formed to insulate a pad on a semiconductor substrate, and a bit line stack formed on the interlayer dielectric layer. The semiconductor memory device includes a pair of bit line spacers, which are formed at both side walls of the bit line stack, and has a storage node contact hole exposing the surface of the pad formed therebetween. In the storage node contact hole, a multi-layered storage node contact plug is formed, in which a first storage node contact plug and a second storage node contact plug are sequentially formed.
Preferably, the first storage node contact plug is formed of a titanium nitride layer and the second storage node contact plug is formed of a polysilicon layer. Preferably, the bit line stack consists of a bit line barrier metal layer, a bit line conductive layer, and a bit line cap layer which are sequentially deposited. Preferably, the bit line barrier metal layer is formed of a titanium nitride layer, the bit line conductive layer is formed of a tungsten layer, and the bit line cap layer is formed of a silicon nitride layer. A barrier metal layer, which acts as a third storage node contact plug, may be further formed on the second storage node contact plug.
To achieve the second object of the present invention, there is provided a method for fabricating a semiconductor memory device including forming a bit line stack on a semiconductor substrate, on which an interlayer dielectric layer for insulating a pad is formed. A pair of bit line spacers are formed at both side walls of the bit line stack. A storage node contact hole is formed to be aligned at the bit line spacers and expose the pad in the interlayer dielectric layer by using a self align contact etching method. A multi-layered storage node contact plug, which consists of a first storage node contact plug and a second node contact plug, is formed in the storage node contact hole.
Preferably, the first storage node contact plug is formed of a titanium nitride layer and the second storage node contact plug is formed of a polysilicon layer. A barrier metal layer, which acts as a third storage node contact plug, may be further formed on the second storage node contact plug.
The multi-layered storage node contact plug is formed by the following steps. A first storage node contact plug material layer is formed on the entire surface of the semiconductor substrate after the storage node contact hole is formed. A second storage node contact plug material layer is formed on the first storage node contact plug material layer to sufficiently fill the storage node contact hole. A second storage node contact plug is formed in the storage node contact hole by etching back the second storage node contact plug material layer. A barrier metal material layer is formed on the entire surface of the semiconductor substrate on which the second storage node contact plug is formed. The first storage node contact plug material layer and the barrier metal material layer on the bit line stack are then etched to complete the multi-layered storage node.